Double side polished wafers having external gettering sites, and method of producing same

ABSTRACT

A semiconductor wafer manufacturing process is disclosed wherein a double side polished wafer having oxygen induced stacking faults to provide extrinsic gettering on the back surface of the wafer. The process includes polishing the back surface of the wafer, and depositing a thin polysilicon film on the polished back surface. The wafer is then subjected to a thermal oxidation step, wherein the polysilicon film is consumed by the thermal oxidation step. The oxide layer is then stripped from the back surface, leaving oxygen induced stacking faults on the back surface of the wafer. The front surface of the wafer is then polished, thereby producing a double side polished wafer containing extrinsic gettering sites on the polished back surface.

FIELD OF THE INVENTION

[0001] The present invention relates generally to a method of processingsemiconductor wafers, and more particularly to a method of processingdouble side polished wafers that contain external gettering sites.

BACKGROUND OF THE INVENTION

[0002] Semiconductor integrated circuits are manufactured by combiningconnected circuit elements, such as transistors, diodes, resistors, andcapacitors, within a continuous substrate wafer, such as a siliconwafer. Manufacturers of integrated circuits are continually trying toimprove performance and reduce the size of semiconductors in order toreduce cost of manufacture, with line widths reaching 0.13 microns orsmaller. This improvement naturally requires improvements in the qualityof the wafers used as the substrate for such circuitry. Some of thefactors that impact the ability to reduce the size of the integratedcircuit include flatness of the substrate wafer and contamination levelsboth within the wafer bulk and on the surfaces of the wafer.

[0003] Semiconductor wafers are manufactured typically by growing amonocrystalline ingot using Float Zone, Ribbon Growth, or more commonly,a Czochralski technique. The ingot is then sliced into individual wafersusing an inner diameter saw where wafers are sliced individually fromthe ingot, or a wire saw wherein the entire ingot is sliced into waferssimultaneously. The wafers are then subjected to an edge profilingprocess to round the edges and remove stress points. A wafer thinningstep is then employed, such as lapping or surface grinding, to bothremove slicing damage from the surfaces of the wafer and to make theopposing surfaces as flat and coplanar as possible. Because much of theequipment used to slice and shape the surfaces of the wafer are metal,and because metallic contaminants negatively effect the quality of anintegrated circuit, the wafer is then subjected to a chemical etching,which removes metal ions from the surfaces of the wafer and assists inremoving the finer surface damage caused by the lapping or surfacegrinding steps. Historically, one side of the wafer has then beenpolished to a mirror-like finish to provide a smooth surface formanufacture of the integrated circuit. This surface that will be usedfor manufacture of the integrated circuit is typically called the “frontside” of the wafer, with the opposing side being called the “back side”of the wafer.

[0004] Because small amounts of metallic impurities are grown into thecrystal originally, an extrinsic gettering method has often been used onthe back side of the wafer to gather and trap these metallic impurities.This extrinsic gettering has typically been accomplished by introducingsmall amounts of damage to the back side of the wafer by varioustechniques such as a wet sand blast. The wafer is then heat treated toallow the metallic impurities to diffuse through the wafer bulk to thedamaged area on the back side of the wafer, where the impurities gatherand are trapped. Another common technique for this extrinsic getteringis to deposit a thin polycrystalline film on the back of the wafer bychemical vapor deposition (CVD), which is performed at elevatedtemperatures, and assists the impurities in diffusing through the waferbulk to the grain boundaries of the polycrystalline silicon, where theyare gettered and trapped. Unfortunately, since there is damage on theback side of the wafer, the damage also acts as a trap for particles andother contaminants in the ambient surroundings of the wafer. Theseparticles may become dislodged at inopportune times, and cause failureor decreased yield in the manufacture of the integrated circuit.

[0005] One of the methods utilized to improve flatness of the substratewafer and simultaneously improve the surface contamination levels ispolishing both sides of the substrate wafer, know as double sidepolishing, or DSP. DSP can be performed by polishing both sides of thewafer simultaneously, or by polishing one side at a time. However, awafer polished on both sides loses extrinsic gettering capabilities. Assuch, efforts have been made to perform partial backside polish, wheresome of the damage, or surface roughness, is removed. This offers someextrinsic gettering abilities, but sacrifices some of the benefitsassociated with double side polishing in that particles can still betrapped in the surface roughness. Conversely, if both sides of thesubstrate wafer are polished to a complete polish, sometimes known as a“mirror polish”, the surface roughness on both sides is reduced to a fewAngstroms or less. This complete polished surface is fine enough toprevent particle trapping, but is so fine that little or no extrinsicgettering is available.

[0006] Therefore, a need exists for a double side polished wafer where acomplete polish is possible on both sides of the wafer, with the waferstill having extrinsic gettering capabilities.

SUMMARY OF THE INVENTION

[0007] The present invention relates to a semiconductor substrate waferwhich has been polished on both sides to a complete or mirror polish butprovides extrinsic gettering on the back side of the wafer, and a methodfor manufacturing such a wafer. In the present invention, asemiconductor substrate wafer is prepared by slicing an ingot intowafers. This slicing can be accomplished by either an inner-diameter sawwhere wafers are sliced sequentially, or by a wire saw, wherein theentire ingot is sliced into multiple wafers simultaneously. The wafer isthen subjected to an edge grinding process, where the periphery of thewafer is chamfered to increase strength and remove sharp edges that caneasily be chipped or broken. Lapping or surface grinding both surfacesof the wafer to remove slicing damage and to make the front and backsurfaces both flat and parallel to each other is next performed on thewafer. After lapping or surface grinding, the wafer is chemicallyetched. Common etchants can be either an acid mixture, such as a mixtureof Nitric, Acetic, and Hydroflouric acids, or a caustic mixture, such asSodium Hydroxide. A sequential etch where first one solution and thenthe other solution is utilized may also be employed. Etching isperformed to remove the damage caused by lapping or surface grinding, toremove metals contamination, and to improve brightness on the wafersurfaces. A wafer identification process, such as a laser markingprocess, may be employed if desired, said process being inserted eitherimmediately before or after the lapping or surface grinding process.

[0008] The back side of the wafer is then polished to a complete, ormirror polish. In this case, a complete or mirror polish on the backside of the wafer as a polish that is no more than 2 times the surfaceroughness or other measurement characteristics as that of the polishedfront side. For example, if the front side of the wafer is polished to asurface roughness of 5 Å, the back side would have a surface roughnessof no more than 10 Å.

[0009] After the back side of the wafer is polished, a thin polysiliconlayer is deposited on the wafer, and the wafer is then subjected to anoxidation step. The oxidation step consumes the polysilicon layer andforms stacking faults at the back surface of the wafer. Once thestacking faults are formed, the oxide layer is then stripped from bothsides of the wafer, and the front side of the wafer is subjected to acomplete polish. This process is useful for all wafer diameters.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 depicts a process flow of one embodiment of the presentinvention wherein stacking faults are formed on both sides of the wafer.

[0011]FIG. 2 depicts a process flow of another embodiment of the presentinvention wherein stacking faults are formed only on the back side ofthe wafer.

[0012]FIG. 3 depicts a modified process flow of the embodiment found inFIG. 1.

[0013]FIG. 4 depicts a modified process flow of the embodiment found inFIG. 2.

DETAILED DESCRIPTION OF THE INVENTION

[0014] The present invention will now be described more fullyhereinafter, in which preferred embodiments of the invention are shown.This invention may, however, be embodied in many different forms andshould not be construed as limited to the embodiments set forth herein.These embodiments are provided so that the disclosure will convey thescope of the invention to those skilled in the art.

[0015] Turning now to FIG. 1, a semiconductor wafer, such as a siliconwafer, is prepared through standard wafer shaping techniques includingslicing the wafer from a crystal ingot, chamfering the periphery of thewafer, lapping or surface grinding the front and back surfaces,chemically etching the surfaces, and polishing the back surface of thewafer to a complete or mirror polish. Multiple cleaning steps, optionalidentification marking steps, and/or inspection steps may be performedas desired. A wafer thus prepared is depicted as 100 on FIG. 1,containing a polished back side 110 and an unpolished front side 120.

[0016] Wafer 100 is then subjected to a process to grow a polysiliconlayer 130 on both the polished back side 110 and the unpolished frontside 120. During growth of the polysilicon layer 130, high levels ofoxygen 132 will be trapped in the grains of the polysilicon layer 130.The polysilicon layer 130 can be in the thickness range of about 50 Å toabout 500 Å, and can be grown using any known method of chemical vapordeposition (CVD), including hot-wall and cold-wall reactors, atmosphericpressure (APCVD) or low pressure (LPCVD), and in single wafer reactorsor in batch reactors.

[0017] Wafer 100 is then subjected to a thermal oxidation step whereinan oxide layer 140 is deposited on the surfaces of the polysilicon layer130. The oxide layer can be in the thickness range of 100 Å to 1000 Å.The limiting factor is the ability for the oxide layer 140 to be able tocompletely “consume” the polysilicon layer 130 such that when the oxidelayer 140 is later stripped from the surface of the wafer 100, oxygeninduced stacking faults (OISF or OSF) 150 remain on the surface of thewafer, but no polysilicon layer 130 exists. A typical thermal oxidationcycle sufficient for the purpose of consuming the polysilicon layer 130can range from about 850° C. to 1000° C., with a duration ofapproximately 30 minutes. As is known in the art, varying temperatureand time settings result in varied oxide layer thicknesses and can beoptimized accordingly.

[0018] After the thermal cycle for the oxide layer 140 is complete, thewafer is subjected to a stripping and cleaning process. A typicalstripping and cleaning process utilizes a hydrofluoric acid (HF) bath,followed by the so-called RCA cleaning, which comprises a first bathcontaining a mixture of water, hydrogen peroxide, and ammonium hydroxide(also known as SC1) followed by a bath containing a mixture of water,hydrogen peroxide, and hydrochloric acid (also known as SC2). The HFbath strips the oxide layer 140 from the wafer, the SC1 bath removesorganic contaminants as well as some Group I and Group II metals, andSC2 removes alkali and transition metals.

[0019] When the oxide layer 140 is stripped from the wafer, and sincethe polysilicon layer 130 was consumed by the oxide layer 140, the backside surface 110 and the front side surface 120 of wafer 100 containstacking faults 150 with a density of up to 3*10⁵ cm⁻². These stackingfaults act as extrinsic gettering sites, where impurities found withinthe wafer will migrate and be trapped.

[0020] The front side 120 of wafer 100 is then subjected to a completepolishing process, which removes the stacking faults 150 from the frontside 120. The surface roughness of the front side 120 and the back side110 are comparable, with both sides having a roughness of about 10 Å orless, yet the back side 110 contains sufficient stacking faults 150 toprovide extrinsic gettering.

[0021]FIG. 2 demonstrates another embodiment, wherein processing stepsare completed in the same fashion as that of the embodiment depicted inFIG. 1. As shown in FIG. 2, however, the polysilicon layer 130 isdeposited only on the back side 110 of the wafer 100. This alternateembodiment can utilize single-side wafer CVD chambers and/or singlewafer processing chambers. Since there is no benefit in gettering orprocessing by having oxygen induced stacking faults on the front surfaceof the wafer, where they would ultimately need to be removed bypolishing, the embodiment of FIG. 2 allows for providing extrinsicgettering capability on the back side of the wafer without anyprocessing of the front side.

[0022] As shown if FIG. 3, another embodiment of the present inventionprovides for forming a polysilicon layer 230 on both the back side 210and front side 220 of wafer 200, wherein the back side 210 haspreviously been subjected to a complete or mirror polish. Thepolysilicon layer 230 has interstitial oxygen through the layer.Thermally induced oxide layers 240 are then grown on both polysiliconlayers 230, wherein the polysilicon layers 230 are consumed by the oxidelayers 240. The oxygen originally contained in the polysilicon layers230 migrates to the wafer surfaces 210 and 220, and forms oxygen inducedstacking faults, 250. The front side 220 of the wafer 200 is thensubjected to a complete or mirror polish process, wherein the oxidelayer 240 is polished off the front side 220, the stacking faults 250are polished off, and then the front surface 220 itself is complete ormirror polished. The back side of the wafer 210 still contains the oxidelayer 240. After the complete polish step is completed on the frontsurface 220, the wafer is then subjected to a strip and clean processwherein HF is used to strip the oxide layer from the back side, and anRCA cleaning is then used to clean the wafer surfaces 210 and 220. Theresultant wafer has a completely polished back side surface 210 thatcontains stacking faults 250 to supply extrinsic gettering, and a frontsurface 220 with a complete polish. The surface roughnesses of both theback surface 210 and the front surface 220 are approximately 10 Å orless. The disadvantage of this embodiment is the added time required topolish away the oxide layer 240, and obviously the thinner the oxidelayer 240 is, the faster the polishing process. The advantage of thisembodiment, however, is the back surface 220 is protected by the oxidelayer 240 from any additional impurities that may be found within thepolishing process, ultimately resulting in a cleaner wafer 200.

[0023] In yet another embodiment, as depicted in FIG. 4, a complete ormirror polished back side 210 of a wafer 200 is subjected to a processfor growing a polysilicon layer 230, again such layer containing oxygen.A thermally grown oxide layer 240 is then grown on the polysilicon layer230. The front side 220 of the wafer 200 is not subjected to either theprocess for growing polysilicon or an oxide layer. At this point, thefront surface 220 of the wafer 200 is subjected to a complete or mirrorpolish. The wafer 200 is then subjected to a stripping and cleaningprocess wherein HF is used to strip the oxide layer 240 off the backsurface 210, leaving stacking faults 250 on the back surface 210. Thewafer cleaning is continued in typical fashion using RCA. The resultantwafer 200 contains a complete or mirror polish on both back and frontsurfaces 210 and 220, having surface roughnesses of 10 Å or less, andwith the back surface 210 having extrinsic gettering capabilities in theform of oxygen induced stacking faults 250 in a density of up to 3*10⁵cm⁻².

[0024] Various changes could be made to any or all of the abovedescribed embodiments of the present invention while still encapsulatingthe inventive scope of the invention. The embodiments provided showexamples of processes for achieving double side polished wafer whereinthe back side of the wafer contains extrinsic gettering, and theinvention is not meant to be limited by such embodiments. As such, thoseskilled in the art can carry out modifications and changes to thespecifically described embodiments without departing from the scope orspirit of the present invention, which is inteded to be limited only theby the scope of the appended claims.

What is claimed is:
 1. A method of producing a double-side polishedwafer containing extrinsic gettering sites on one side, comprising:providing a semiconductor wafer, said wafer having a front surface and aback surface, wherein the back surface has been polished; forming apolysilicon layer on the front surface and the back surface, saidpolysilicon layers containing oxygen; forming a thermal oxide layer oneach of the polysilicon layers, wherein the oxide layers consume thepolysilicon layers; stripping the thermal oxide layers off of the wafer;and polishing the front side of the wafer.
 2. The method of claim 1,wherein the back surface contains oxygen induced stacking faults toserve as extrinsic gettering sites.
 3. The method of claim 2 wherein theback surface contains at least 5*10⁴ oxygen induced stacking faults persquare centimeter.
 4. The method of claim 1, wherein the polysiliconlayers are between 50 Å and 500 Å in thickness.
 5. The method of claim4, wherein the polysilicon layers are deposited by chemical vapordeposition.
 6. The method of claim 5 wherein the polysilicon layers aredeposited by low pressure chemical vapor deposition.
 7. The method ofclaim 1, wherein the thermal oxide layers are between 100 Å and 1000 Åin thickness.
 8. The method of claim 1 wherein the thermal-oxide layersare formed at a temperature of between 850° C. and 1000° C.
 9. Themethod of claim 1, wherein each of the back and front surfaces have asurface roughness of below 10 Å after polishing the front side of thewafer.
 10. A method of producing a double-side polished wafer containingextrinsic gettering sites on one side, comprising: providing asemiconductor wafer, said wafer having a front surface and a backsurface, wherein the back surface has been polished; forming apolysilicon layer on the back surface, said polysilicon layer containingoxygen; forming a thermal oxide layer on the polysilicon layer, whereinthe oxide layer consumes the polysilicon layer; stripping the thermaloxide layer off of the wafer; and polishing the front side of the wafer.11. The method of claim 10, wherein the back surface contains oxygeninduced stacking faults to serve as extrinsic gettering sites.
 12. Themethod of claim 10 wherein the back surface contains at least 5*10⁴oxygen induced stacking faults per square centimeter.
 13. The method ofclaim 10, wherein the polysilicon layer is between 50 Å and 500 Å inthickness.
 14. The method of claim 13, wherein the polysilicon layer isdeposited by chemical vapor deposition.
 15. The method of claim 14wherein the polysilicon layer is deposited by low pressure chemicalvapor deposition.
 16. The method of claim 10, wherein the thermal oxidelayer is between 100 Å and 1000 Å in thickness.
 17. The method of claim10 wherein the thermal oxide layer is formed at a temperature of between850° C. and 1000° C.
 18. The method of claim 10, wherein each of theback and front surfaces have a surface roughness of below 10 Å afterpolishing the front side of the wafer.
 19. A method of producing adouble-side polished wafer containing extrinsic gettering sites on oneside, comprising: providing a semiconductor wafer, said wafer having afront surface and a back surface, wherein the back surface has beenpolished; forming a polysilicon layer on the front surface and the backsurface, said polysilicon layers containing oxygen; forming a thermaloxide layer on each of the polysilicon layers, wherein the oxide layersconsume the polysilicon layers; polishing the front side of the wafer;and stripping the thermal oxide layer off of the back surface of thewafer.
 20. The method of claim 19, wherein the back surface containsoxygen induced stacking faults to serve as extrinsic gettering sites.21. The method of claim 20 wherein the back surface contains at least5*10⁴ oxygen induced stacking faults per square centimeter.
 22. Themethod of claim 19, wherein the polysilicon layers are between 50 Å and500 Å in thickness.
 23. The method of claim 22, wherein the polysiliconlayers are deposited by chemical vapor deposition.
 24. The method ofclaim 23, wherein the chemical vapor deposition process is a lowpressure chemical vapor deposition.
 25. The method of claim 19, whereinthe thermal oxide layers are between 100 Å and 1000 Å in thickness. 26.The method of claim 19 wherein the thermal oxide layers are formed at atemperature of between 850° C. and 1000° C.
 27. The method of claim 19,wherein each of the back and front surfaces have a surface roughness ofbelow 10 Å after polishing the front side of the wafer.
 28. A method ofproducing a double-side polished semiconductor wafer containingextrinsic gettering sites on one side, comprising: providing asemiconductor wafer, said wafer having a front surface and a backsurface, wherein the back surface has been polished; forming apolysilicon layer on the back surface, said polysilicon layer containingoxygen; forming a thermal oxide layer on the polysilicon layer, whereinthe oxide layer consumes the polysilicon layer; polishing the front sideof the wafer; and stripping the thermal oxide layer off of the backsurface of the wafer.
 29. The method of claim 28, wherein the backsurface contains oxygen induced stacking faults to serve as extrinsicgettering sites.
 30. The method of claim 28 wherein the back surfacecontains at least 5*10⁴ oxygen induced stacking faults per squarecentimeter.
 31. The method of claim 28, wherein the polysilicon layer isbetween 50 Å and 500 Å in thickness.
 32. The method of claim 31, whereinthe polysilicon layer is deposited by chemical vapor deposition.
 33. Themethod of claim 32 wherein the polysilicon layer is deposited by lowpressure chemical vapor deposition.
 34. The method of claim 28, whereinthe thermal oxide layer is between 100 Å and 1000 Å in thickness. 35.The method of claim 28 wherein the thermal oxide layer is formed at atemperature of between 850° C. and 1000° C.
 36. The method of claim 28,wherein each of the back and front surfaces have a surface roughness ofbelow 10 Å after polishing the front side of the wafer.
 37. Adouble-side polished semiconductor wafer containing extrinsic getteringsites on a back surface of the wafer, prepared by a process comprisingthe steps of: providing a semiconductor wafer, said wafer having a frontsurface and a back surface, wherein the back surface has been polished;forming a polysilicon layer on the front surface and the back surface,said polysilicon layers containing oxygen; forming a thermal oxide layeron each of the polysilicon layers, wherein the oxide layers consume thepolysilicon layers; stripping the thermal oxide layers off of the wafer;and polishing the front side of the wafer.
 38. A double-side polishedsemiconductor wafer containing extrinsic gettering sites on a backsurface of the wafer, prepared by a process comprising the steps of:providing a semiconductor wafer, said wafer having a front surface and aback surface, wherein the back surface has been polished; forming apolysilicon layer on the back surface, said polysilicon layer containingoxygen; forming a thermal oxide layer on the polysilicon layer, whereinthe oxide layer consumes the polysilicon layer; stripping the thermaloxide layer off of the wafer; and polishing the front side of the wafer.39. A double-side polished semiconductor wafer containing extrinsicgettering sites on a back surface of the wafer, prepared by a processcomprising the steps of: providing a semiconductor wafer, said waferhaving a front surface and a back surface, wherein the back surface hasbeen polished; forming a polysilicon layer on the front surface and theback surface, said polysilicon layers containing oxygen; forming athermal oxide layer on each of the polysilicon layers, wherein the oxidelayers consume the polysilicon layers; polishing the front side of thewafer; and stripping the thermal oxide layer off of the back surface ofthe wafer.
 40. A double-side polished semiconductor wafer containingextrinsic gettering sites on a back surface of the wafer, prepared by aprocess comprising the steps of: providing a semiconductor wafer, saidwafer having a front surface and a back surface, wherein the backsurface has been polished; forming a polysilicon layer on the backsurface, said polysilicon layer containing oxygen; forming a thermaloxide layer on the polysilicon layer, wherein the oxide layer consumesthe polysilicon layer; polishing the front side of the wafer; andstripping the thermal oxide layer off of the back surface of the wafer.